In What Way Are General Purpose Registers And Main Memory Similar

Full general-Purpose Register

Cortex-M3 Basics

Joseph Yiu , in The Definitive Guide to the ARM Cortex-M3 (Second Edition), 2010

iii.1 Registers

As we've seen, the Cortex™-M3 processor has registers R0 through R15 and a number of special registers. R0 through R12 are general purpose, but some of the 16-bit Pollex^® instructions can only access R0 through R7 (low registers), whereas 32-chip Thumb-2 instructions can access all these registers. Special registers accept predefined functions and tin can only be accessed by special register access instructions.

3.1.1 Full general Purpose Registers R0 through R7

The R0 through R7 general purpose registers are also chosen low registers. They can exist accessed by all 16-bit Thumb instructions and all 32-bit Thumb-two instructions. They are all 32 bits; the reset value is unpredictable.

3.i.two General Purpose Registers R8 through R12

The R8 through R12 registers are also chosen high registers. They are attainable by all Thumb-two instructions but not past all sixteen-bit Pollex instructions. These registers are all 32 bits; the reset value is unpredictable (come across Figure 3.1).

FIGURE three.1. Registers in the Cortex-M3.

3.1.3 Stack Pointer R13

R13 is the stack pointer (SP). In the Cortex-M3 processor, at that place are two SPs. This duality allows two split stack memories to be set. When using the register proper name R13, y'all tin only access the current SP; the other one is inaccessible unless you use special instructions to movement to special register from full general-purpose register (MSR) and motion special annals to general-purpose register (MRS). The two SPs are as follows:

•

Master Stack Pointer (MSP) or SP_main in ARM documentation: This is the default SP; it is used by the operating arrangement (Bone) kernel, exception handlers, and all application codes that require privileged access.

•

Process Stack Arrow (PSP) or SP_process in ARM documentation: This is used by the base-level application code (when not running an exception handler).

Stack PUSH and POP

Stack is a memory usage model. It is simply role of the system retentiveness, and a pointer annals (inside the processor) is used to go far work equally a first-in/last-out buffer. The common use of a stack is to salve annals contents before some data processing then restore those contents from the stack after the processing task is done.

Figure 3.ii. Basic Concept of Stack Memory.

When doing Push button and POP operations, the pointer register, commonly chosen stack pointer, is adjusted automatically to forestall next stack operations from corrupting previous stacked data. More details on stack operations are provided on after office of this chapter.

It is not necessary to use both SPs. Uncomplicated applications tin rely purely on the MSP. The SPs are used for accessing stack memory processes such every bit PUSH and Pop.

In the Cortex-M3, the instructions for accessing stack retentivity are PUSH and Popular. The assembly linguistic communication syntax is every bit follows (text later each semicolon [;] is a comment):

Push   {R0}   ; R13=R13-4, and then Memory[R13] = R0

POP   {R0}   ; R0 = Memory[R13], then R13 = R13 + 4

The Cortex-M3 uses a full-descending stack arrangement. (More than detail on this subject field tin can be found in the "Stack Retentiveness Operations" section of this affiliate.) Therefore, the SP decrements when new data is stored in the stack. PUSH and Pop are usually used to salve register contents to stack memory at the start of a subroutine and so restore the registers from stack at the end of the subroutine. You tin can Push or POP multiple registers in ane instruction:

subroutine_1

  PUSH   {R0-R7, R12, R14} ; Relieve registers

  ...   ; Practice your processing

  POP   {R0-R7, R12, R14} ; Restore registers

  BX   R14   ; Render to calling function

Instead of using R13, you can utilise SP (for SP) in your program codes. It means the same thing. Inside program lawmaking, both the MSP and the PSP tin can exist called R13/SP. However, you tin can access a item 1 using special register admission instructions (MRS/MSR).

The MSP, also called SP_main in ARM documentation, is the default SP after ability-up; it is used by kernel lawmaking and exception handlers. The PSP, or SP_process in ARM documentation, is typically used past thread processes in organization with embedded OS running.

Because annals PUSH and POP operations are e'er word aligned (their addresses must be 0x0, 0x4, 0x8, ...), the SP/R13 flake 0 and bit 1 are hardwired to 0 and always read as cypher (RAZ).

3.1.4 Link Annals R14

R14 is the link annals (LR). Inside an assembly program, you lot can write it equally either R14 or LR. LR is used to store the return program counter (PC) when a subroutine or part is called—for case, when you're using the branch and link (BL) instruction:

main   ; Main plan

  ...

  BL function1 ; Phone call function1 using Co-operative with Link educational activity.

  ; PC = function1 and

  ; LR = the next didactics in main

  ...

function1

  ...   ; Programme code for function ane

  BX LR   ; Return

Despite the fact that bit 0 of the PC is always 0 (because instructions are give-and-take aligned or one-half word aligned), the LR bit 0 is readable and writable. This is because in the Thumb instruction set, bit 0 is often used to bespeak ARM/Thumb states. To permit the Thumb-ii program for the Cortex-M3 to piece of work with other ARM processors that support the Thumb-two engineering, this to the lowest degree significant bit (LSB) is writable and readable.

3.1.5 Program Counter R15

R15 is the PC. Yous can access it in assembler code by either R15 or PC. Because of the pipelined nature of the Cortex-M3 processor, when yous read this register, yous will find that the value is unlike than the location of the executing instruction, normally by 4. For instance:

0x1000 :   MOV   R0, PC   ; R0 = 0x1004

In other instructions like literal load (reading of a memory location related to current PC value), the effective value of PC might not be instruction address plus four due to alignment in address calculation. But the PC value is all the same at least two bytes alee of the didactics address during execution.

Writing to the PC will crusade a branch (but LRs exercise not get updated). Because an instruction address must exist one-half word aligned, the LSB (bit 0) of the PC read value is e'er 0. However, in branching, either past writing to PC or using branch instructions, the LSB of the target address should exist set to 1 because it is used to indicate the Pollex state operations. If information technology is 0, information technology can imply trying to switch to the ARM state and will issue in a fault exception in the Cortex-M3.

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INTRODUCTION TO THE ARM Educational activity Set

ANDREW N. SLOSS , ... CHRIS WRIGHT , in ARM System Programmer's Guide, 2004

3.5 Program Condition Annals INSTRUCTIONS

The ARM instruction ready provides two instructions to directly control a program status register (psr). The MRS instruction transfers the contents of either the cpsr or spsr into a register; in the contrary management, the MSR instruction transfers the contents of a register into the cpsr or spsr. Together these instructions are used to read and write the cpsr and spsr.

In the syntax you tin see a label called fields. This can be whatsoever combination of control (c), extension (x), status (s), and flags (f). These fields relate to particular byte regions in a psr, every bit shown in Figure 3.9.

Effigy 3.9. psr byte fields.

MRS	re-create plan status register to a general-purpose annals	Rd = psr
MSR	move a general-purpose annals to a programme status register	psr[field] = Rm
MSR	move an firsthand value to a program status register	psr[field] = immediate

The c field controls the interrupt masks, Thumb state, and processor mode. Example 3.26 shows how to enable IRQ interrupts past clearing the I mask. This performance involves using both the MRS and MSR instructions to read from and then write to the cpsr.

EXAMPLE 3.26

The MSR first copies the cpsr into annals r1. The BIC educational activity clears flake 7 of r1. Register r1 is then copied dorsum into the cpsr, which enables IRQ interrupts. You lot can run across from this instance that this code preserves all the other settings in the cpsr and merely modifies the I bit in the control field.

This example is in SVC mode. In user manner yous can read all cpsr bits, but you tin merely update the condition flag field f.

3.5.one COPROCESSOR INSTRUCTIONS

Coprocessor instructions are used to extend the educational activity set. A coprocessor can either provide additional computation capability or be used to command the memory subsystem including caches and memory management. The coprocessor instructions include data processing, register transfer, and memory transfer instructions. Nosotros volition provide but a curt overview since these instructions are coprocessor specific. Annotation that these instructions are but used by cores with a coprocessor.

CDP	coprocessor data processing—perform an operation in a coprocessor
MRC MCR	coprocessor register transfer—move data to/from coprocessor registers
LDC STC	coprocessor memory transfer—load and store blocks of memory to/from a coprocessor

In the syntax of the coprocessor instructions, the cp field represents the coprocessor number between p0 and p15. The opcode fields draw the performance to take identify on the coprocessor. The Cn, Cm, and Cd fields describe registers within the coprocessor. The coprocessor operations and registers depend on the specific coprocessor you are using. Coprocessor 15 (CP15) is reserved for arrangement control purposes, such equally retention management, write buffer control, cache control, and identification registers.

EXAMPLE three.27

This instance shows a CP15 register being copied into a general-purpose annals.

Here CP15 register-0 contains the processor identification number. This annals is copied into the general-purpose register r10.

iii.5.2 COPROCESSOR 15 Educational activity SYNTAX

CP15 configures the processor core and has a set up of defended registers to store configuration information, as shown in Example 3.27. A value written into a register sets a configuration attribute—for example, switching on the cache.

CP15 is chosen the organization command coprocessor. Both MRC and MCR instructions are used to read and write to CP15, where annals Rd is the core destination annals, Cn is the primary register, Cm is the secondary register, and opcode2 is a secondary register modifier. You may occasionally hear secondary registers called "extended registers."

As an example, here is the didactics to move the contents of CP15 control register c1 into register r1 of the processor core:

Nosotros apply a shorthand note for CP15 reference that makes referring to configuration registers easier to follow. The reference notation uses the post-obit format:

The first term, CP15, defines information technology equally coprocessor 15. The 2d term, subsequently the separating colon, is the primary annals. The primary register 10 can have a value between 0 and 15. The third term is the secondary or extended register. The secondary register Y can accept a value between 0 and 15. The terminal term, opcode2, is an instruction modifier and can have a value between 0 and seven. Some operations may also utilize a nonzero value w of opcode1. We write these as CP15:w:cX:cY:Z.

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Overview of the Cortex-M3

Joseph Yiu , in The Definitive Guide to the ARM Cortex-M3 (Second Edition), 2010

2.2 Registers

The Cortex-M3 processor has registers R0 through R15 (run across Figure two.2). R13 (the stack arrow) is banked, with only 1 re-create of the R13 visible at a fourth dimension.

Effigy 2.2. Registers in the Cortex-M3.

ii.two.1 R0–R12: Full general-Purpose Registers

R0–R12 are 32-bit full general-purpose registers for information operations. Some xvi-bit Thumb ^® instructions can only access a subset of these registers (depression registers, R0–R7).

2.2.two R13: Stack Pointers

The Cortex-M3 contains two stack pointers (R13). They are banked so that only i is visible at a time. The two stack pointers are equally follows:

•

Main Stack Pointer (MSP): The default stack pointer, used by the operating system (OS) kernel and exception handlers

•

Process Stack Arrow (PSP): Used past user application code

The everyman 2 bits of the stack pointers are always 0, which means they are ever discussion aligned.

2.ii.3 R14: The Link Register

When a subroutine is chosen, the return address is stored in the link register.

ii.two.4 R15: The Program Counter

The program counter is the current program address. This annals tin be written to control the program flow.

two.two.5 Special Registers

The Cortex-M3 processor also has a number of special registers (see Figure ii.3). They are as follows:

•

Plan Status registers (PSRs)

•

Interrupt Mask registers (PRIMASK, FAULTMASK, and BASEPRI)

•

Command register (CONTROL)

FIGURE 2.3. Special Registers in the Cortex-M3.

These registers have special functions and can exist accessed just by special instructions. They cannot be used for normal data processing (run into Table 2.ane).

Table 2.1. Special Registers and Their Functions

Register	Function
xPSR	Provide arithmetics and logic processing flags (zero flag and carry flag), execution status, and electric current executing interrupt number
PRIMASK	Disable all interrupts except the nonmaskable interrupt (NMI) and difficult mistake
FAULTMASK	Disable all interrupts except the NMI
BASEPRI	Disable all interrupts of specific priority level or lower priority level
CONTROL	Ascertain privileged status and stack arrow selection

For more information on these registers, see Chapter 3.

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Early Intel® Architecture

In Power and Functioning, 2015

one.one.2 Registers

Bated from the four segment registers introduced in the previous department, the 8086 has vii general purpose registers, and two status registers.

The full general purpose registers are divided into ii categories. Iv registers, AX, BX, CX, and DX, are classified equally information registers. These data registers are attainable as either the full 16-fleck register, represented with the X suffix, the low byte of the total 16-bit annals, designated with an Fifty suffix, or the high byte of the 16-bit register, delineated with an H suffix. For instance, AX would access the full 16-bit register, whereas AL and AH would access the register'due south low and loftier bytes, respectively.

The 2nd classification of registers are the pointer/index registers. This includes the post-obit four registers: SP, BP, SI, and DI, The SP annals, the stack pointer, is reserved for usage as a pointer to the top of the stack. The SI and DI registers are typically used implicitly equally the source and destination pointers, respectively. Unlike the information registers, the pointer/index registers are only accessible as full 16-bit registers.

Every bit this categorization may signal, the general purpose registers come with some guidance for their intended usage. This guidance is reflected in the instruction forms with implicit operands. Instructions with implicit operands, that is, operands which are causeless to be a certain register and therefore don't require that operand to be encoded, let for shorter encodings for common usages. For convenience, instructions with implicit forms typically also have explicit forms, which require more bytes to encode. The recommended uses for the registers are as follows:

AX Accumulator

BX Data (relative to DS)

CX Loop counter

DX Data

SI Source pointer (relative to DS)

DI Destination arrow (relative to ES)

SP Stack pointer (relative to SS)

BP Base of operations pointer of stack frame (relative to SS)

Bated from allowing for shorter teaching encodings, this guidance is also an aid to the programmer who, one time familiar with the diverse register meanings, will exist able to deduce the meaning of assembly, assuming it conforms to the guidelines, much faster. This parallels, to some degree, how variable names help the programmer reason virtually their contents. It's of import to note that these are just suggestions, not rules.

Additionally, there are 2 status registers, the instruction arrow and the flags register.

The instruction arrow, IP, is too often referred to equally the program counter. This register contains the memory address of the next pedagogy to be executed. Until 64-chip fashion was introduced, the instruction pointer was non directly accessible to the programmer, that is, it wasn't possible to access information technology like the other general purpose registers. Despite this, the pedagogy arrow was indirectly accessible. Whereas the instruction arrow couldn't be modified through a MOV pedagogy, information technology could be modified by any instruction that alters the programme flow, such as the Call or JMP instructions.

Reading the contents of the educational activity arrow was also possible by taking advantage of how x86 handles function calls. Transfer from one function to another occurs through the Telephone call and RET instructions. The Telephone call education preserves the current value of the instruction arrow, pushing information technology onto the stack in order to support nested function calls, and and then loads the didactics arrow with the new address, provided every bit an operand to the educational activity. This value on the stack is referred to as the return address. Whenever the part has finished executing, the RET instruction pops the return address off of the stack and restores information technology into the instruction pointer, thus transferring control dorsum to the function that initiated the office call. Leveraging this, the developer tin can create a special thunk function that would simply re-create the return value off of the stack, load it into 1 of the registers, and then render. For example, when compiling Position-Independent-Lawmaking (Pic), which is discussed in Chapter 12, the compiler volition automatically add functions that use this technique to obtain the pedagogy pointer. These functions are usually called __x86.get_pc_thunk.bx(), __x86.get_pc_thunk.cx(), __x86.get_pc_thunk.dx(), and then on, depending on which annals the didactics pointer is loaded.

The 2nd condition register, the EFLAGS register, is comprised of 1-chip status and control flags. These $.25 are set by various instructions, typically arithmetic or logic instructions, to point certain conditions. These condition flags can then be checked in club to make decisions. For a list of the flags modified by each education, see the Intel SDM. The 8086 defined the following status and control $.25 in EFLAGS:

Nil Flag (ZF) Set if the result of the teaching is aught.

Sign Flag (SF) Set up if the result of the instruction is negative.

Overflow Flag (OF) Set if the result of the education overflowed.

Parity Flag (PF) Set if the consequence has an even number of $.25 set.

Bear Flag (CF) Used for storing the carry bit in instructions that perform arithmetics with carry (for implementing extended precision).

Arrange Flag (AF) Similar to the Deport Flag. In the parlance of the 8086 documentation, this was referred to as the Auxiliary Bear Flag.

Management Flag (DF) For instructions that either autoincrement or autodecrement a arrow, this flag chooses which to perform. If set, autodecrement, otherwise autoincrement.

Interrupt Enable Flag (IF) Determines whether maskable interrupts are enabled.

Trap Flag (TF) If set CPU operates in unmarried-pace debugging mode.

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Intel® Pentium® Processors

In Power and Performance, 2015

Annals Renaming

From the didactics set up perspective, Intel processors have eight full general purpose registers in 32-bit mode, and 16 general purpose registers in 64-bit fashion, yet, from the internal hardware perspective, Intel processors take many more than registers. For example, the Pentium Pro has xl registers, organized in a structure referred to as a Physical Annals File.

While this many extra registers might seem like a performance benefaction, especially if the reader is familiar with the performance gain received from the 8 extra registers in 64-scrap mode, these registers serve a dissimilar purpose. Rather than providing the process with more than registers, these actress registers serve to handle information dependencies in the out-of-order execution engine.

When a value is stored into a register, a new register file entry is assigned to incorporate that value. Once another value is stored into that register, a different register file entry is assigned to contain this new value. Internal to the processor core, each data dependency on the first value volition reference the first entry, and each information dependency on the second value volition reference the second entry. Therefore, the out-of-guild engine is able to execute instructions in an order that would otherwise exist impossible due to imitation information dependencies.

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Load/store and branch instructions

Larry D. Pyeatt , William Ughetta , in ARM 64-Bit Associates Language, 2020

iii.2 AArch64 user registers

As shown in Fig. 3.2 , the AArch64 ISA provides 31 general-purpose registers, which are called

through

. These registers can each store 64 bits of information. To utilise all 64 bits, they are referred to equally

through

(capitalization is optional). To employ but the lower (least meaning) 32 bits, they are referred to as

. Since each register has a 64-flake name and a 32-chip name, nosotros use

through

to specify a register without specifying the number of bits. For example, when we refer to

, nosotros are really referring to either

or

.

Figure iii.2. AArch64 general purpose registers (

) and special registers.

three.2.i General purpose registers

The full general-purpose registers are each used according to specific conventions. These rules are defined in the awarding binary interface (ABI). The AArch64 ABI is called AAPCS64. The divergence between callee saved and caller saved registers will also be explained in Section 5.4.4.

Registers

are used for passing arguments when calling a process or function Registers

are scratch registers and can be used at whatsoever time because no assumptions are made almost what they contain. They are called scratch registers because they are useful for holding temporary results of calculations. Registers

can likewise be used as scratch registers, but their contents must be saved before they are used, and restored to their original contents before the process exits.

Some of the registers have alternate names. For example,

is also known every bit

. Near of these alternate names are simply of interest to people writing compilers and operating systems. Yet, two of these registers are of involvement to all AArch64 programmers.

three.ii.ii Frame pointer

The frame arrow,

, is used past loftier-level language compilers to track the current stack frame. This annals can be helpful when the plan is running under a debugger, and can sometimes help the compiler to generate more efficient code for returning from a subroutine. The GNU C compiler can exist instructed to employ

as a general-purpose register by using the –fomit-frame-pointer control line option. The utilize of

as the frame pointer is a programming convention. Some instructions (e.thou. branches) implicitly change the programme counter, the link annals, and even the stack pointer, so they are considered to be hardware special registers. As far equally the hardware is concerned, the frame arrow is exactly the aforementioned as the other full general-purpose registers, simply AArch64 programmers use it for the frame pointer because of the ABI.

3.2.3 PSTATE register

The

annals contains bits that indicate the condition of the current process, including data nigh the results of previous operations. Fig. iii.3 shows all of its $.25. The dashed lines signal unused infinite that may be reserved for future AArch64 architectural extensions. The

register is actually a drove of independent fields, virtually of which are just used by the operating system. User programs make use of the first four bits, N, Z, C, and V. These are referred to as the status flags field. Most instructions can modify these flags, and subsequently instructions tin can use the flags to control their operation. Their meaning is as follows:

Negative:

This scrap is set to ane if the signed outcome of an operation is negative, and set up to zero if the effect is positive or nothing.

Goose egg:

This bit is fix to one if the effect of an operation is zilch, and gear up to zero if the upshot is not-zero.

Carry:

This bit is ready to one if an add operation results in a carry out of the most significant bit, or if a subtract operation results in a infringe. For shift operations, this flag is set to the last flake shifted out by the shifter.

oVerflow:

For add-on and subtraction, this flag is set up if a signed overflow occurred.

Figure three.3. Fields in the PSTATE annals.

3.two.4 Link register

The procedure link annals,

, is used to hold the return accost for subroutines. Certain instructions cause the programme counter to be copied to the link register, so the program counter is loaded with a new accost. These branch-and-link instructions are briefly covered in Section three.5 and in more item in Department five.4. The link annals could theoretically be used equally a scratch register, only its contents are modified by hardware when a subroutine is called, in order to salve the right render address. Using

every bit a general-purpose register is unsafe and is strongly discouraged.

three.2.v Stack arrow

The program stack was introduced in Section one.4. The stack arrow,

, is used to agree the address where the stack ends. This is normally referred to as the top of the stack, although on virtually systems the stack grows downward and the stack pointer actually refers to the lowest address in the stack. The accost where the stack ends may modify when registers are pushed onto the stack, or when temporary local variables (automated variables) are allocated or deleted. The use of the stack for storing automatic variables is described in Chapter 5. The stack pointer tin can but be modified or read by a small ready of instructions.

iii.two.6 Zero annals

The nil register,

, can be referred to as a 64-bit register,

, or a 32-bit annals,

. Information technology always has the value zero. Nigh instructions can utilize the zero annals as an operand, fifty-fifty equally a destination register. If this is the case, the instruction will not alter the destination register. However, it can nevertheless take side effects, including updating the

flags based on the ALU operation and incrementing a register in pre-indexed or post-indexed addressing. The zippo annals cannot ever be used as an operand. It shares the aforementioned binary encoding with the stack pointer register,

, which is the value

. Some instructions tin can access the nada register, while others can admission the stack arrow.

3.2.vii Program counter

The program counter,

, e'er contains the accost of the side by side instruction that will be executed. The processor increments this register by four, automatically, after each pedagogy is fetched from memory. Past moving an address into this register, the programmer tin cause the processor to fetch the adjacent instruction from the new address. This gives the developer the power to jump to any accost and begin executing code in that location. Only a small number of instructions can access the

directly. For example instructions that create a PC-relative accost, such as

, and instructions which load a register, such as

, are able to access the program counter straight.

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Knights Landing architecture

Jim Jeffers , ... Avinash Sodani , in Intel Xeon Phi Processor High Operation Programming (Second Edition), 2016

Integer execution unit

The IEU executes integer μops, which are divers as those that operate on general-purpose registers R0–R15 (i.e., RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI, R8…R15). In that location are two IEUs in the core. Each IEU contains 12-entry RS that issues i μop per wheel. The Integer RSes are fully out-of-lodge in their scheduling. Most operations have i-bike latency and are supported by both IEUs, but a few operations accept 3- or 5-cycles latency (east.g., multiplies) and are only supported by one of the IEUs.

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Computer Information Processing Hardware Architecture

Paul J. Fortier , Howard E. Michel , in Reckoner Systems Performance Evaluation and Prediction, 2003

two.3.i Instruction types

Based on the number of registers available and the configuration of these registers several types of pedagogy are possible—for example, if many registers are available, as would exist the case in a stack computer, no address computations are needed and the education, therefore, can be much shorter both in format and execution fourth dimension required. On the other hand, if there are no general registers and all computations are performed by memory movements of data, then instructions will be longer and require more time due to operand fetching and storage. The following are representative of educational activity types:

0-address instructions—This type of instruction is found in machines where many general-purpose registers are available. This is the case in stack machines and in some reduced instruction set machines. Instructions of this type perform their function totally using registers. If we have 3 general registers, A, B, and C, a typical format would have the form:

(2.one) $R\left[A\right]<--R\left[B\right]\text{operator}R\left[C\right]$

which indicates that the contents of registers B and C have the operator (such as add, subtract, multiply, etc.) performed on them, with the result stored in general register C. Similarly, we could describe instructions that use just one or two registers equally follows:

(2.ii) $R\left[B\right]<--R\left[B\right]\text{operator}R\left[C\right]$

or

(two.three) $\text{operator}R\left[C\right]$

which represents two-register and one-register instructions, respectively. In the 2-register case one of the operand registers is also used every bit the result annals. In the single-register instance the operand register is too the upshot annals. The increment instruction is an example of 1-register instruction. This type of educational activity is found in all machines.

1-address instructions—In this blazon of didactics a unmarried retentiveness address is found in the educational activity. If another operand is used, information technology is typically an accumulator or the top of a stack in a stack computer. The typical format of these instructions has the course:

(2.four) $\text{operator}M\left[\text{address}\right]$

where the contents of the named memory address accept the named operator performed on them in conjunction with an implied special register. An example of such an didactics could exist equally follows:

(two.five) $\text{Move}\mathrm{One\; thousand}\left[100\right]$

or

(2.six) $\text{Add together}M\left[100\right]$

which moves the contents of retention location 100 into the ALU's accumulator or adds the contents of memory accost 100 with the accumulator and stores the result in the accumulator. If the event must be stored in memory, nosotros would need a store education:

(ii.7) $\text{Shop}M\left[100\right]$

1-and-l/2-address instructions—Once nosotros have an architecture that has some general-purpose registers, we tin provide more than advanced operations combining memory contents and the general registers. The typical instruction performs an operation on a retentiveness location's contents with that of a full general register—for instance, nosotros could add the contents of a retentiveness location with the contents of a full general register, A, as shown:

(two.8) $\text{Add together}R\left[A\right],M\left[100\right]$

This instruction typically stores the outcome in the offset named location or register in the instruction. In this instance it is register A.

two-address instructions—Two address instructions utilize two memory locations to perform an education—for example, a cake move of N words from one location in retentiveness to another, or a block add. The move may appear as follows:

(2.9) $\text{Move}N,\mathrm{One\; thousand}\left[100\right],M\left[\mathrm{one\; thousand}\right]$

ii-and-l/2-address instructions—This format uses ii retentiveness locations and a general annals in the instruction. Typical of this type of instruction is an operation involving two retention locations storing the result in a register or an performance with a general register and a retentivity location storing the event on some other memory location, as shown:

(2.10) $\begin{array}{l}R\left[A\right]-->>M\left[100\right]\text{operator}M\left[\mathrm{m}\right]\\ M\left[1000\right]-->>\mathrm{Yard}\left[100\right]\text{operator}R\left[A\right]\end{array}$

iii-accost instructions—Another less common form of instruction format is the iii-accost instruction. These instructions involve three memory locations—two used for operands and ane every bit the results location. A typical format is shown:

(two.11) $\mathrm{Grand}\left[200\right]-->>\mathrm{1000}\left[100\right]\text{operator}M\left[300\right]$

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Advanced Encryption Standard

Tom St Denis , Simon Johnson , in Cryptography for Developers, 2007

x86 Performance

The AMD Opteron achieves a overnice boost due to the addition of the eight new general-purpose registers. If we examine the GCC output for x86_64 and x86_32 platforms, we tin see a dainty deviation between the two ( Table 4.two).

Table 4.2. First Quarter of an AES Round

Both snippets accomplish (at least) the starting time MixColumns footstep of the first round in the loop. Note that the compiler has scheduled part of the second MixColumns during the first to attain higher parallelism. Fifty-fifty though in Table 4.2 the x86_64 code looks longer, it executes faster, partially because it processes more of the second MixColumns in roughly the aforementioned time and makes proficient employ of the extra registers.

From the x86_32 side, we tin can clearly run into various spills to the stack (in assuming). Each of those costs us three cycles (at a minimum) on the AMD processors (ii cycles on about Intel processors). The 64-bit code was compiled to have zero stack spills during the main loop of rounds. The 32-bit code has virtually 15 stack spills during each round, which incurs a punishment of at least 45 cycles per circular or 405 cycles over the course of the 9 full rounds.

Of form, we practice not come across the total penalty of 405 cycles, every bit more than 1 opcode is existence executed at the aforementioned fourth dimension. The penalty is too masked by parallel loads that are also on the critical path (such equally loads from the Te tables or circular key). Those delays occur anyways, and so the fact that we are also loading (or storing to) the stack at the same time does not add to the bicycle count.

In either case, nosotros can better upon the lawmaking that GCC (4.1.1 in this case) emits. In the 64-bit code, we see a pairing of "shrq $24, %rdx" and "and1 $255,%edx". The andl operation is not required since only the lower 32 bits of %rdx are guaranteed to have anything in them. This potentially saves up to 36 cycles over the course of nine rounds (depending on how the andl functioning pairs upwards with other opcodes).

With the 32-bit code, the double loads from (%esp) (lines 2 and 3) incur a needless 3-cycle penalty. In the case of the AMD Athlon (and Opterons), the load shop unit volition brusque the load operation (in sure circumstances), but the load will always take at least iii cycles. Changing the second load to "movl %edx,%ebx" means that we stall waiting for %edx, merely the penalty is only one cycle, not three. That change alone will gratis upwardly at most 9*ii*four = 72 cycles from the 9 rounds.

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Embedded Processor Architecture

Peter Barry , Patrick Crowley , in Modern Embedded Computing, 2012

Register Operands

Source and destination operands can be any of the follow registers depending on the instruction being executed:

•

32-scrap general purpose registers (EAX, EBC, ECX, EDX, ESI, EDI, ESP, or EBP)

•

16-bit general purpose registers (AX, BX, CX, DX, SI, SP, BP)

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viii-scrap general-purpose registers (AH, BH, CH, DH, AL, BL, CL, DL)

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Segment registers

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EFLAGS register

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MMX

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Control (CR0 through CR4)

•

System Tabular array registers (such as the Interrupt Descriptor Table register)

•

Debug registers

•

Motorcar-specific registers

On RISC embedded processors, there are generally fewer limitations in the registers that tin can be used by instructions. IA-32 often reduces the registers that can be used as operands for certain instructions.

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In What Way Are General Purpose Registers And Main Memory Similar,

Source: https://www.sciencedirect.com/topics/computer-science/general-purpose-register

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